In recent years, continuing advancements have been made in size and weight reduction, high performance and high functionality of electronic devices such as personal computers, cellular phones, wireless base stations, optical communication devices, servers and routers, of various sizes. With the increasing speeds and higher performance of LSIs such as CPUs, DSPs and various memory chips, development has also been carried out on high-density mounting techniques such as SoC (System on a chip) and SiP (System In Package).
Build-up system-type multilayer circuit boards are therefore being employed on semiconductor chip-mounting substrates and motherboards. With advancements in mounting technologies such as multi-pin and narrow-pitch formation on packages, semiconductor chip-mounting substrates have been shifting from QFP (Quad Flat Package) to BGA (Ball Grid Array)/CSP (Chip Size Package) mounting.
Connection between semiconductor chip-mounting substrates and semiconductor chips is accomplished using gold wire bonding, for example. Semiconductor chip-mounting substrates connected with semiconductor chips are also connected with circuit boards (motherboards) by solder balls. Substrates for mounting semiconductor chips usually have connecting terminals for connection with semiconductor chips or circuit boards. Most connecting terminals are gold plated to ensure satisfactory metal bonding with gold wire or solder.
Electrolytic gold plating has been widely employed in the prior art as a method of gold plating connecting terminals. However, with the recent increase in high density of wirings due to smaller substrates for mounting semiconductor chips, it is becoming difficult to secure the wirings for forming electrolytic gold plating on connecting terminal surfaces. Processes of electroless gold plating (displacement gold plating or reduction gold plating), that do not require lead wires for electrolytic plating, are therefore attracting interest as methods of gold plating onto connecting terminals. For example, formation of an electroless nickel plating film/electroless gold plating films on the copper foil surfaces of terminal sections is known, as described in Non-patent document 1.
However, it is known that in electroless nickel plating/electroless gold plating methods, the solder connection reliability or post-heat treatment wire bondability is reduced, compared to electrolytic nickel plating/electrolytic gold plating methods, as taught in Non-patent document 2.
In addition, electroless nickel plating on wirings produces a phenomenon of deposition of the electroless nickel plating film between wirings, known as “bridging”, which can sometimes cause short circuiting. In order to inhibit bridging, there have been proposed pretreatment solutions and pretreatment methods designed to prevent bridging, as disclosed in Patent documents 1 and 2, for example. There have also been disclosed electroless plating catalyst solutions to prevent bridging, as in Patent document 3.